1. Field of the Invention
This application relates to a large scale integrated circuit that suppresses power noise.
2. Description of the Related Art
Recently, in response to a request for low power consumption, such a technology has been used that the operation frequency is dynamically changed depending on the usage situation of a large scale integrated circuit (hereinafter, referred to as an LSI) and unnecessary power consumption is reduced. For example, when the LSI is not frequently used, a clock frequency is dropped close up to the operation frequency at the necessary and minimal level for data processing in order to reduce unnecessary power consumption. On the other hand, when high-speed processing is required, the clock frequency is raised to meet processing performance. A series of operations are dynamically executed on the LSI, thereby performing required process and reducing the total power consumption.
A resonant frequency is determined depending on power line inductance L and power decoupling capacitance C in the LSI. This technique is disclosed in Japanese Laid-open Patent Publication No. H11-7330.